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Testing Computer Hardware through Data Compression in Space and Time., and . ITC, page 83-88. IEEE Computer Society, (1983)A Data Compression Technique for Built-In Self-Test., , and . IEEE Trans. Computers, 37 (9): 1151-1156 (1988)Correction: IEEE Transactions on Computers 38(2): 320 (1989).Modeling Detection Latency with Collaborative Mobile Sensing Architecture., , and . IEEE Trans. Computers, 58 (5): 692-705 (2009)Hypergraph Coloring and Reconfigured RAM Testing., and . IEEE Trans. Computers, 43 (6): 725-736 (1994)Instruction-based delay fault self-testing of pipelined processor cores., , , and . ISCAS (6), page 5686-5689. IEEE, (2005)Analytic modeling of detection latency in mobile sensor networks., , and . IPSN, page 194-201. ACM, (2006)A Tutorial on Built-In Self-Test, Part 2: Applications., , and . IEEE Des. Test Comput., 10 (2): 69-77 (1993)Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools., , , , and . IEICE Trans. Inf. Syst., 91-D (3): 690-699 (2008)Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment., , , and . IEICE Trans. Inf. Syst., 96-D (6): 1323-1331 (2013)Delay Fault Testing of Processor Cores in Functional Mode., , , and . IEICE Trans. Inf. Syst., 88-D (3): 610-618 (2005)