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Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets.

A. Yan, J. Zhou, Y. Hu, J. Cui, Z. Huang, P. Girard, и X. Wen. IEEE Access, (2019)

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Zhengfeng Zhang

Zhengfeng Qian

Feiqing Huang

Ying Huang

Haishi Huang

Другие публикации лиц с тем же именем

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications.A. Yan, Z. Xu, K. Yang, J. Cui, Z. Huang, P. Girard, и X. Wen. IEEE Trans. Aerosp. Electron. Syst., 56 (4): 2666-2676 (2020)CC-RTSV: Cross-Cellular Based Redundant TSV Design for 3D ICs.T. Ni, Y. Shu, H. Chang, L. Lu, G. Dai, S. Zhu, C. Qu, и Z. Huang. J. Circuits Syst. Comput., 29 (11): 2050144:1-2050144:19 (2020)A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications.A. Yan, K. Qian, T. Song, Z. Huang, T. Ni, Y. Chen, и X. Wen. Integr., (2022)Valid test pattern identification for VLSI adaptive test.T. Song, T. Ni, Z. Huang, и J. Wan. Integr., (2022)Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications.A. Yan, Z. Fan, L. Ding, J. Cui, Z. Huang, Q. Wang, H. Zheng, P. Girard, и X. Wen. IEEE Trans. Aerosp. Electron. Syst., 58 (1): 517-529 (2022)Method of generating strategic guidance information for driving evacuation flows to approach safety-based system optimal dynamic flows: Case study of a large stadium.G. Ren, Z. Huang, L. Lu, J. Hua, и J. Wang. J. Systems Science & Complexity, 28 (3): 606-622 (2015)A high performance SEU-tolerant latch for nanoscale CMOS technology.Z. Huang. DATE, стр. 1-5. European Design and Automation Association, (2014)A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells.Z. Song, A. Yan, J. Cui, Z. Chen, X. Li, X. Wen, C. Lai, Z. Huang, и H. Liang. ITC-Asia, стр. 139-144. IEEE, (2019)Design of Wireless Network on Chip with Priority-Based MAC.Y. Ouyang, Y. Zhao, K. Xing, Z. Huang, H. Liang, и J. Li. Journal of Circuits, Systems, and Computers, 28 (8): 1950124:1-1950124:18 (2019)Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS.A. Yan, Z. Huang, X. Fang, Y. Ouyang, и H. Deng. Microelectron. J., (2017)

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Please choose a person to relate this publication to

Zhengfeng Zhang

Zhengfeng Qian

Feiqing Huang

Ying Huang

Haishi Huang

Другие публикации лиц с тем же именем

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