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Disambiguation of "Wen, Xiaoqing"

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A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications.

, , , , , , and . IEEE Trans. Aerosp. Electron. Syst., 56 (4): 2666-2676 (2020)

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Xiaoqing Pan

Xiaoqing Liu

Xiaoqing Li

Xiaoqing Shen

Xiaoqing Jin

 

Other publications of authors with the same name

Power-aware test generation with guaranteed launch safety for at-speed scan testing., , , , , , , and . VTS, page 166-171. IEEE Computer Society, (2011)Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications., , , and . DATE, page 1679-1684. IEEE, (2019)Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets., , , , , , and . IEEE Access, (2019)LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2938-2951 (2020)HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications., , , , , , , and . DAC, page 1-6. IEEE, (2020)Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (11): 1767-1776 (2009)A Method to Detect Bit Flips in a Soft-Error Resilient TCAM., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (6): 1185-1196 (2018)Trusted fingerprint localization for multimedia devices based on blockchain., , , , and . Inf. Sci., (2023)Power supply noise and its reduction in at-speed scan testing.. ASICON, page 1-4. IEEE, (2015)Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing., , , , , and . DAC, page 527-532. IEEE, (2007)