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Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators.

, , , , , , , , , , , and . ASPLOS, page 369-383. ACM, (2020)ASPLOS 2020 was canceled because of COVID-19..

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Compiling Halide Programs to Push-Memory Accelerators., , , , , , , , , and 1 other author(s). CoRR, (2021)Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators., , , , , , , , , and 2 other author(s). ASPLOS, page 369-383. ACM, (2020)ASPLOS 2020 was canceled because of COVID-19..Low-overhead implementation of logic encryption using gate replacement techniques., , , , and . ISQED, page 257-263. IEEE, (2017)Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (7): 1370-1383 (2018)Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators., , , , , , , and . ACM Trans. Archit. Code Optim., 20 (2): 26:1-26:26 (June 2023)AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers., , , , , , , , , and 23 other author(s). ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (March 2023)FASTrust: Feature analysis for third-party IP trust verification., , , , , , , and . ITC, page 1-10. IEEE, (2015)Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , and 13 other author(s). VLSI Technology and Circuits, page 70-71. IEEE, (2022)Automating System Configuration., , , , , , and . FMCAD, page 102-111. IEEE, (2021)