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Disambiguation of "Raina, Priyanka"

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Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators.

, , , , , , , , , , , and . ASPLOS, page 369-383. ACM, (2020)ASPLOS 2020 was canceled because of COVID-19..

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Mohit Ajitkumar Raina

Robert Anton Rainalter

Priyanka Nannapaneni

Priyanka Shahi

Raina Yamamoto

 

Other publications of authors with the same name

Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains., , , , , , , , , and 1 other author(s). ACM Trans. Reconfigurable Technol. Syst., 16 (2): 26:1-26:28 (June 2023)Best Papers From Hot Chips 32., and . IEEE Micro, 41 (2): 6 (2021)Simba: scaling deep-learning inference with chiplet-based architecture., , , , , , , , , and 7 other author(s). Commun. ACM, 64 (6): 107-116 (2021)Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , and 13 other author(s). VLSI Technology and Circuits, page 70-71. IEEE, (2022)Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture., , , , , , , , , and 7 other author(s). MICRO, page 14-27. ACM, (2019)Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators., , , , , , , and . ACM Trans. Archit. Code Optim., 20 (2): 26:1-26:26 (June 2023)AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers., , , , , , , , , and 23 other author(s). ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (March 2023)A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs., , , , , , , , , and . DATE, page 846-851. IEEE, (2020)Timeloop: A Systematic Approach to DNN Accelerator Evaluation., , , , , , , , , and . ISPASS, page 304-315. IEEE, (2019)