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Disambiguation of "Talegaonkar, Mrunmay"

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A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery.

, , , , , and . IEEE J. Solid State Circuits, 46 (12): 3163-3173 (2011)

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Other publications of authors with the same name

An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS., , , , , and . IEEE J. Solid State Circuits, 49 (10): 2228-2242 (2014)A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links., , , , , and . IEEE J. Solid State Circuits, 50 (12): 3101-3119 (2015)A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time., , , , and . ISSCC, page 256-257. IEEE, (2013)3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS., , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 10-25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition., , , , , , , and . IEEE J. Solid State Circuits, 51 (2): 428-439 (2016)A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation., , , , , , and . IEEE J. Solid State Circuits, 53 (3): 884-895 (2018)A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links., , , , and . IEEE J. Solid State Circuits, 49 (10): 2243-2258 (2014)A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver., , , , , , , and . IEEE J. Solid State Circuits, 52 (5): 1399-1411 (2017)A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method., , , , , , , , and . IEEE J. Solid State Circuits, 50 (4): 882-895 (2015)