( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS.

, , , , и . ISCAS, стр. 1-5. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Andrea Witzenrath

Risikofaktoren für abdominelle Komplikationen nach kardiopulmonalem Bypass. Uni Erlangen-Nürnberg, (2009)

Andrea Rottach

Analysis of the cell cycle dependent dynamics of Dnmt1 and Np95 in living cells. Uni München, (2009)

Andrea Hruby

Die MAPKKK Bck1p des Zellwand-Integritätssignalwegs in der Bäckerhefe Saccharomyces cerevisiae. Uni Münster, (2009)

Michaela Andrea Fingas

Resultate nach radikaler Prostatektomie bei Patienten mit einem Prostatakarzinom Gleason 7-10. Uni Marburg, (2009)

Andrea Calker

 

Другие публикации лиц с тем же именем

Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions., , , , и . ACM Great Lakes Symposium on VLSI, стр. 253-258. ACM, (2015)Power modeling and characterization of Graphene-based logic gates., , , и . PATMOS, стр. 223-226. IEEE, (2013)Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing., , , , , и . DATE, стр. 1544-1549. EDA Consortium, San Jose, CA, USA, (2007)Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores., , , и . ICECS, стр. 598-601. IEEE, (2019)EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets., , и . AICAS, стр. 233-237. IEEE, (2020)Adaptive Test-Time Augmentation for Low-Power CPU., , , , и . CoRR, (2021)Design Techniques and Architectures for Low-Leakage SRAMs., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (9): 1992-2007 (2012)Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 1979-1993 (2009)Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (3): 406-418 (2013)Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits., , , и . ISLPED, стр. 217-220. ACM, (2008)