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Built-In Test for Hidden Delay Faults.

, , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1956-1968 (2019)

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Synthesis of Self-Testable Controllers., and . EDAC-ETC-EUROASIC, page 580-585. IEEE Computer Society, (1994)Analyzing and quantifying fault tolerance properties.. LATW, page 1. IEEE Computer Society, (2013)Fast Self-Recovering Controllers., , and . VTS, page 296-302. IEEE Computer Society, (1998)Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study., , , and . DFT, page 1-6. IEEE, (2020)Are Robust Circuits Really Robust?, and . DFT, page 77-77. IEEE Computer Society, (2009)The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems., and . DFT, page 101-108. IEEE Computer Society, (2010)Efficient Online and Offline Testing of Embedded DRAMs., , , , and . IEEE Trans. Computers, 51 (7): 801-809 (2002)Synthese vollstaendig testbarer Schaltungen. Karlsruhe University, Germany, (1991)base-search.net (ftubkarlsruhe:oai:EVASTAR-Karlsruhe.de:25491).Symmetric Transparent BIST for RAMs., , and . DATE, page 702-707. IEEE Computer Society / ACM, (1999)Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs., , and . DATE, page 173-179. IEEE Computer Society, (1998)