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High performance and memory efficient implementation of matrix multiplication on FPGAs.

, , and . FPT, page 134-137. IEEE, (2010)

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Automatic synthesis of processor arrays with local memories on FPGAs., , and . FPT, page 249-252. IEEE, (2010)Instruction Selection for Subword Level Parallelism Optimizations for Application Specific Instruction Processors., , and . ISPA, volume 4742 of Lecture Notes in Computer Science, page 946-957. Springer, (2007)High-Performance Architecture for the Conjugate Gradient Solver on FPGAs., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (11): 791-795 (2013)A coarse-grained reconfigurable computing architecture with loop self-pipelining., , , and . Sci. China Ser. F Inf. Sci., 52 (4): 575-587 (2009)A High Performance and Memory Efficient LU Decomposer on FPGAs., , , and . IEEE Trans. Computers, 61 (3): 366-378 (2012)High performance and memory efficient implementation of matrix multiplication on FPGAs., , and . FPT, page 134-137. IEEE, (2010)Topgun: An ECC Accelerator for Private Set Intersection., , , , , , , , , and . ACM Trans. Reconfigurable Technol. Syst., 16 (4): 52:1-52:30 (December 2023)FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing., , , , , and . ICS, page 325-336. ACM, (2010)A Unified Co-Processor Architecture for Matrix Decomposition., , , , , and . J. Comput. Sci. Technol., 25 (4): 874-885 (2010)Computation rotating for data reuse., , , and . ACSAC, page 1-7. IEEE Computer Society, (2008)