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An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems., , и . FPL, стр. 47-53. IEEE, (2007)Region-based caching: an energy-delay efficient memory architecture for embedded processors., и . CASES, стр. 120-127. ACM, (2000)Adaptive transaction scheduling for transactional memory systems., и . SPAA, стр. 169-178. ACM, (2008)Kicking the tires of software transactional memory: why the going gets tough., , , , , и . SPAA, стр. 265-274. ACM, (2008)Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV., , и . IEEE Trans. Very Large Scale Integr. Syst., 21 (1): 1-13 (2013)Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs., , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (1): 38-52 (2007)Profile-guided microarchitectural floor planning for deep submicron processor design., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (7): 1289-1300 (2006)Chameleon: Virtualizing idle acceleration cores of a heterogeneous multicore processor for caching and prefetching., , , и . ACM Trans. Archit. Code Optim., 7 (1): 3:1-3:35 (2010)Information Flow Control in Machine Learning through Modular Model Architecture., , , , , , , , , и . CoRR, (2023)SimWare: A Holistic Warehouse-Scale Computer Simulator., и . Computer, 45 (9): 48-55 (2012)