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Другие публикации лиц с тем же именем

The Best Flip-Flops to Scan., , и . ITC, стр. 166-173. IEEE Computer Society, (1991)Test compaction for sequential circuits., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (2): 260-267 (1992)Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (5): 531-546 (1995)Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (9): 1141-1154 (1995)Synchronous Test Generation Model for Asynchronous Circuits., , и . VLSI Design, стр. 178-185. IEEE Computer Society, (1996)Impact of Partial Reset on Fault Independent Testing and BIST., , и . VLSI Design, стр. 537-539. IEEE Computer Society, (1997)T5: Low-Power Design., , , и . VLSI Design, стр. 4. IEEE Computer Society, (1997)Initialization Isuues in the Synthesis of Asynchronous Circuits., , , и . ICCD, стр. 447-452. IEEE Computer Society, (1994)Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters., и . ICCD, стр. 606-609. IEEE Computer Society, (1993)EDA challenges facing future microprocessor design., , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (12): 1498-1506 (2000)