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Disambiguation of "Leupers, Rainer"

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Direct FPGA-based power profiling for a RISC processor.

, , , , , , , , and . I2MTC, page 1578-1583. IEEE, (2015)

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Rainer Leupers

Rainer Leupers

Rainer Leupers

Rainer Melzer

Multimerisierung und DNA-Bindung homöotischer Proteine der Blütenbildung. Uni Jena, (2009)

Rainer Nustede

In-vitro-Proliferationsverhalten pädiatrischer Tumorzelllinien nach zweistündiger Exposition mit Kohlenstoffdioxid, Helium und Raumluft. MedH Hannover, (2009)
 

Other publications of authors with the same name

Split-cost communication model for improved MPSoC application mapping., , , , and . ISSoC, page 1-8. IEEE, (2013)Software Compilation Techniques for MPSoCs., , and . Handbook of Signal Processing Systems, Springer, (2010)Combined MPSoC Task Mapping and Memory Optimization for Low-Power., , , and . APCCAS, page 121-124. IEEE, (2019)An optimal allocation of memory buffers for complex multicore platforms., , , and . J. Syst. Archit., (2016)Time-constrained code compaction for DSPs., and . IEEE Trans. Very Large Scale Integr. Syst., 5 (1): 112-122 (1997)A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (9): 706-710 (2010)Compiler Design Issues for Embedded Processors.. IEEE Des. Test Comput., 19 (4): 51-58 (2002)Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (6): 1716-1729 (2022)Retargetable compiler technology for embedded systems - tools and applications., and . Kluwer, (2001)A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding, , , , and . CoRR, (2009)