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Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis., , , , , , and . Int. J. Embed. Real Time Commun. Syst., 2 (3): 1-20 (2011)Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs., , , , , , and . IEEE Embed. Syst. Lett., 11 (3): 93-96 (2019)Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model., , , , and . ACM Trans. Embed. Comput. Syst., 16 (1): 26:1-26:26 (2016)AMAIX: A Generic Analytical Model for Deep Learning Accelerators., , , , and . SAMOS, volume 12471 of Lecture Notes in Computer Science, page 36-51. Springer, (2020)Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables., , and . ISSRE, page 127-137. IEEE, (2020)VLSI implementation of linear MIMO detection with boosted communications performance: extended abstract., , , and . ACM Great Lakes Symposium on VLSI, page 71-72. ACM, (2014)Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem., , , , , and . VEHITS, page 59-69. SciTePress, (2018)A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding, , , , and . CoRR, (2009)Enhanced structural analysis for C code reconstruction from IR code., , , , and . SCOPES, page 21-27. ACM, (2011)Trends in embedded software synthesis., , and . ICSAMOS, page 347-354. IEEE, (2011)