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Disambiguation of "Miryala, Sandeep"

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Design and Challenges of Edge Computing ASICs on Front-End Electronics.

, , , , , , , , and . ISQED, page 19-27. IEEE, (2022)

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Sandeep Sadanandan

Sandeep Nambiar

Sandeep Kumar

Sandeep Ameta

Sandeep Pal

 

Other publications of authors with the same name

An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies., , , and . ISQED, page 665-669. IEEE, (2013)NBTI effects on tree-like clock distribution networks., , , , , and . ACM Great Lakes Symposium on VLSI, page 279-282. ACM, (2012)Peak Prediction Using Multi Layer Perceptron (MLP) for Edge Computing ASICs Targeting Scientific Applications., , , , , , , , , and 1 other author(s). ISQED, page 1-6. IEEE, (2022)Exploration of different implementation styles for graphene-based reconfigurable gates., , , and . ICICDT, page 21-24. IEEE, (2013)Delay model for reconfigurable logic gates based on graphene PN-junctions., , , and . ACM Great Lakes Symposium on VLSI, page 227-232. ACM, (2013)A verilog-a model for reconfigurable logic gates based on graphene pn-junctions., , , , and . DATE, page 877-880. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Schottky-barrier graphene nanoribbon field-effect transistors-based field-programmable gate array's configurable logic block and routing switch., , and . IET Circuits Devices Syst., 11 (6): 549-558 (2017)CAD Solutions for Graphene Based Nanoelectronic Circuits and Systems.. Polytechnic University of Turin, Italy, (2014)Investigation of Timing Properties for an Event Driven with Access and Reset Decoder Readout Architecture for a Pixel Array., , and . PRIME, page 113-116. IEEE, (2022)An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (4): 2311-2315 (2022)