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Disambiguation of "Kim, Chulwoo"

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A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology.

, , , , , , , , and . IEEE J. Solid State Circuits, 47 (1): 131-140 (2012)

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Ky ng Kim

Die Artikelstruktur in passiven zweisprachigen Wörterbüchern Deutsch-Koreanisch: Konzeption zur Erstellung eines zweisprachigen Lernerwörterbuchs Deutsch-Koreanisch. Uni Heidelberg, (2008)

Kim Gerber

Bongcheol Kim

Youngsang Kim

Ryong Kim

 

Other publications of authors with the same name

A 5-Bit 500-MS/S Flash ADC using Time-Domain Comparison., , , , and . Journal of Circuits, Systems, and Computers, (2012)A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC., , , , , and . ISSCC, page 184-595. IEEE, (2007)An on-chip soft-start technique of current-mode DC-DC converter for biomedical applications., , , and . APCCAS, page 500-503. IEEE, (2010)A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (10): 1461-1469 (2009)Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces., and . IEEE Trans. Very Large Scale Integr. Syst., 22 (4): 701-711 (2014)An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (10): 2156-2163 (2014)A 1-mW Solar-Energy-Harvesting Circuit Using an Adaptive MPPT With a SAR and a Counter., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (6): 331-335 (2013)A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (1): 331-342 (2018)A Single-Inductor Eight-Channel Output DC-DC Converter With Time-Limited Power Distribution Control and Single Shared Hysteresis Comparator., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (12): 3354-3367 (2013)A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM., , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (10): 1207-1211 (2017)