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A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology.

, , , , , , , , and . IEEE J. Solid State Circuits, 47 (1): 131-140 (2012)

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Sense amplifier with offset mismatch calibration for sub 1-V DRAM core operation., and . ISCAS, page 3501-3504. IEEE, (2010)A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface., , , , , , , , , and 6 other author(s). ISCAS, page 3861-3864. IEEE, (2010)A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology., , , , , , , , and . IEEE J. Solid State Circuits, 47 (1): 131-140 (2012)Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster., , , and . SoCC, page 79-82. IEEE, (2010)A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology., , , , , , , , and . ISSCC, page 502-504. IEEE, (2011)A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture., , , , , , , , , and 12 other author(s). ISSCC, page 40-41. IEEE, (2012)An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface., , , , , , , and . ISSCC, page 312-313. IEEE, (2013)A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface., , , , , , , , , and 1 other author(s). ISSCC, page 48-50. IEEE, (2012)A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS., , , , , , , , , and 14 other author(s). ISSCC, page 140-141. IEEE, (2009)25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV., , , , , , , , , and 7 other author(s). ISSCC, page 432-433. IEEE, (2014)