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A correctness criterion for asynchronous circuit validation and optimization.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (11): 1309-1318 (1994)

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Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes., , , and . DAC, page 77-82. ACM Press, (1996)An error-correcting unordered code and hardware support for robust asynchronous global communication., and . DATE, page 765-770. IEEE Computer Society, (2010)A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems., , and . DATE, page 332-337. EDA Consortium San Jose, CA, USA / ACM DL, (2013)An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (7): 1043-1056 (2010)Synthesis for logical initializability of synchronous finite-state machines., and . IEEE Trans. Very Large Scale Integr. Syst., 8 (5): 542-557 (2000)Guest Editorial., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (6): 662-664 (2003)Exact two-level minimization of hazard-free logic with multiple-input changes., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (8): 986-997 (1995)A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input Sample Rate., , , and . IEEE J. Solid State Circuits, 49 (10): 2292-2304 (2014)OPTIMIST: state minimization for optimal 2-level logic implementation., and . ICCAD, page 308-315. IEEE Computer Society / ACM, (1997)Practicality of state-machine verification of speed-independent circuits., and . ICCAD, page 266-269. IEEE Computer Society, (1989)