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A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems.

, , and . DATE, page 332-337. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies., , , , , and . ASP-DAC, page 337-342. IEEE, (2014)A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems., , and . DATE, page 332-337. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems., , , , , , and . NOCS, page 170-171. IEEE, (2014)A feature-rich NoC switch with cross-feature optimizations for the next generation of reliable and reconfigurable embedded systems., , , and . INA-OCMC@HiPEAC, page 2:1-2:4. ACM, (2014)System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic., , , and . VLSI-SoC, page 308-313. IEEE, (2011)Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study., , , and . VLSI-SoC, page 1-6. IEEE, (2014)Methodologies and Toolflows for the Predictable Design of Reliable and Low-Power NoCs.. University of Ferrara, Italy, (2014)Power efficiency of switch architecture extensions for fault tolerant NoC design., , , and . IGCC, page 1-6. IEEE Computer Society, (2012)Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs., , , , and . CODES+ISSS, page 181-186. ACM, (2012)Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems., , , , , , , and . IEEE Micro, 41 (1): 69-81 (2021)