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13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.

J. Lee, K. Cho, C. Lee, Y. Lee, J. Park, S. Oh, Y. Ju, C. Jeong, H. Cho, J. Lee, T. Yun, J. Cho, S. Oh, J. Moon, Y. Park, H. Choi, I. Kim, S. Yang, S. Kim, J. Jang, J. Kim, S. Lee, Y. Jeon, J. Park, T. Kim, D. Ka, S. Oh, J. Kim, J. Jeon, S. Kim, K. Kim, T. Kim, H. Yang, D. Yang, M. Lee, H. Song, D. Jang, J. Shin, H. Kim, C. Baek, H. Jeong, J. Yoon, S. Lim, K. Lee, Y. Koo, M. Park, J. Cho, and J. Kim. ISSCC, page 238-240. IEEE, (2024)

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Su-Jeong Jeong

Wonrae Jeong

Hyung-Gon Jeong

Hang-Kyun Jeong

Chang-Kyo Jeong

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Newton: A DRAM-maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning.M. He, C. Song, I. Kim, C. Jeong, S. Kim, I. Park, M. Thottethodi, and T. Vijaykumar. MICRO, page 372-385. IEEE, (2020)A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application.D. Kwon, S. Lee, K. Kim, S. Oh, J. Park, G. Hong, D. Ka, K. Hwang, J. Park, K. Kang and 27 other author(s). IEEE J. Solid State Circuits, 58 (1): 291-302 (2023)IANUS: Integrated Accelerator based on NPU-PIM Unified Memory System.M. Seo, X. Nguyen, S. Hwang, Y. Kwon, G. Kim, C. Park, I. Kim, J. Park, J. Kim, W. Shin and 11 other author(s). ASPLOS (3), page 545-560. ACM, (2024)13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.J. Lee, K. Cho, C. Lee, Y. Lee, J. Park, S. Oh, Y. Ju, C. Jeong, H. Cho, J. Lee and 38 other author(s). ISSCC, page 238-240. IEEE, (2024)Memory-Centric Computing with SK Hynix's Domain-Specific Memory.Y. Kwon, G. Kim, N. Kim, W. Shin, J. Won, H. Joo, H. Choi, B. An, G. Shin, D. Yun and 17 other author(s). HCS, page 1-26. IEEE, (2023)A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications.S. Lee, K. Kim, S. Oh, J. Park, G. Hong, D. Ka, K. Hwang, J. Park, K. Kang, J. Kim and 21 other author(s). ISSCC, page 1-3. IEEE, (2022)Holistic approaches to memory solutions for the Autonomous Driving Era.D. Shim, C. Jeong, E. Lee, J. Kang, S. Yoon, Y. Kwon, I. Park, H. Ahn, S. Cha, and J. Kim. ISCAS, page 351-355. IEEE, (2022)A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller.S. Lee, B. Jeon, K. Kang, D. Ka, N. Kim, Y. Kim, Y. Hong, M. Kang, J. Min, M. Lee and 19 other author(s). ISSCC, page 384-386. IEEE, (2019)18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface.J. Lee, J. Kim, K. Kim, Y. Ku, D. Kim, C. Jeong, T. Yun, H. Kim, H. Cho, Y. Kim and 12 other author(s). ISSCC, page 318-319. IEEE, (2016)High bandwidth memory(HBM) with TSV technique.J. Lee, J. Kim, K. Kim, Y. Ku, D. Kim, C. Jeong, T. Yun, H. Kim, H. Cho, S. Oh and 9 other author(s). ISOCC, page 181-182. IEEE, (2016)

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Disambiguation of "Jeong, Chunseok"

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13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.

Please choose a person to relate this publication to

Su-Jeong Jeong

Wonrae Jeong

Hyung-Gon Jeong

Hang-Kyun Jeong

Chang-Kyo Jeong

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Jeong, Chunseok"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.

Please choose a person to relate this publication to

Su-Jeong Jeong

Wonrae Jeong

Hyung-Gon Jeong

Hang-Kyun Jeong

Chang-Kyo Jeong

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.