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13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.

J. Lee, K. Cho, C. Lee, Y. Lee, J. Park, S. Oh, Y. Ju, C. Jeong, H. Cho, J. Lee, T. Yun, J. Cho, S. Oh, J. Moon, Y. Park, H. Choi, I. Kim, S. Yang, S. Kim, J. Jang, J. Kim, S. Lee, Y. Jeon, J. Park, T. Kim, D. Ka, S. Oh, J. Kim, J. Jeon, S. Kim, K. Kim, T. Kim, H. Yang, D. Yang, M. Lee, H. Song, D. Jang, J. Shin, H. Kim, C. Baek, H. Jeong, J. Yoon, S. Lim, K. Lee, Y. Koo, M. Park, J. Cho, and J. Kim. ISSCC, page 238-240. IEEE, (2024)

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Jinhyung Park

Xavier Lee Lee

Bongsoo Lee

The role of negative regulators in coordination of the Myxococcus xanthus developmental programB. Lee. Uni Marburg, (2009)

Min-Hi Lee

Induction and regulation of antiviral defence mechanisms through intracytoplasmic sensorsM. Lee. HU Berlin, (2009)

Sangbok Lee

Other publications of authors with the same name

Job Accessibility as a Lens for Understanding the Urban Structure of Colonial Cities: A Digital Humanities Study of the Colonial Seoul in the 1930s Using GIS.Y. Kim, J. Kim, H. Ha, N. Nakajima, and J. Lee. ISPRS Int. J. Geo Inf., 11 (12): 614 (December 2022)A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration.M. Choo, S. Kim, H. Ko, S. Cho, K. Park, J. Lee, S. Shin, H. Chi, and D. Jeong. IEEE J. Solid State Circuits, 56 (8): 2525-2538 (2021)Predicting households' residential mobility trajectories with geographically localized interpretable model-agnostic explanation (GLIME).C. Jin, S. Park, H. Ha, J. Lee, J. Kim, J. Hutchenreuther, and A. Nara. Int. J. Geogr. Inf. Sci., 37 (12): 2597-2619 (December 2023)A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS.K. Park, W. Bae, J. Lee, J. Hwang, and D. Jeong. IEEE J. Solid State Circuits, 53 (10): 2982-2993 (2018)A theoretical analysis of phase shift in pulse injection-locked oscillators.J. Lee, S. Kim, M. Choo, S. Cho, H. Ko, and D. Jeong. ISCAS, page 1662-1665. IEEE, (2016)Discrete Neural ProcessesA. Pakman, Y. Wang, C. Mitelut, J. Lee, and L. Paninski. (2018)cite arxiv:1901.00409.A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation.H. Joo, J. Lee, H. Ju, H. Ko, J. Yoon, B. Kang, and D. Jeong. IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2708-2720 (2020)A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.M. Park, H. Cho, T. Yun, S. Byeon, Y. Koo, S. Yoon, D. Lee, S. Choi, J. Park, J. Lee and 39 other author(s). ISSCC, page 444-446. IEEE, (2022)A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS.C. Kye, H. Ko, J. Lee, and D. Jeong. IEEE Trans. Very Large Scale Integr. Syst., 28 (5): 1099-1106 (2020)25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections.G. Jeong, J. Hwang, H. Choi, H. Do, D. Koh, D. Yun, J. Lee, K. Park, H. Ko, K. Lee and 3 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 65-II (10): 1395-1399 (2018)

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Disambiguation of "Lee, Jinhyung"

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13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.

Please choose a person to relate this publication to

Jinhyung Park

Xavier Lee Lee

Bongsoo Lee

Min-Hi Lee

Sangbok Lee

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lee, Jinhyung"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.

Please choose a person to relate this publication to

Jinhyung Park

Xavier Lee Lee

Bongsoo Lee

Min-Hi Lee

Sangbok Lee

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.