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Disambiguation of "Dinakarrao, Sai Manoj Pudukotai"

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POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications.

, , , , and . DSD, page 889-898. IEEE, (2022)

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Slavica Manojlovic

Sai Li

Manoj Kakkassery

Manoj Khanal

Sai Zhang

 

Other publications of authors with the same name

Unified Testing and Security Framework for Wireless Network-on-Chip Enabled Multi-Core Chips., , , and . ACM Trans. Embed. Comput. Syst., 18 (5s): 75:1-75:20 (2019)Cyber-physical management for heterogeneously integrated 3D thousand-core on-chip microprocessor., and . ISCAS, page 533-536. IEEE, (2013)Deep Multi-attributed Graph Translation with Node-Edge Co-Evolution., , , , , and . ICDM, page 250-259. IEEE, (2019)Evolution of Defenses against Transient-Execution Attacks., , , and . ACM Great Lakes Symposium on VLSI, page 169-174. ACM, (2020)Session details: Session 7A: Special Session - 3: Machine Learning-Aided Computer-Aided Design.. ACM Great Lakes Symposium on VLSI, ACM, (2022)Defense Against on-Chip Trojans Enabling Traffic Analysis Attacks., , , , , , and . AsianHOST, page 1-6. IEEE, (2020)POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications., , , , and . DSD, page 889-898. IEEE, (2022)SAT to SAT-Hard Clause Translator., , , and . CASES (work in progress), page 1-2. IEEE, (2019)Q-Learning-Based Voltage-Swing Tuning and Compensation for 2.5-D Memory-Logic Integration., , , , and . IEEE Des. Test, 35 (2): 91-99 (2018)Weighted Quantization-Regularization in DNNs for Weight Memory Minimization Toward HW Implementation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (11): 2929-2939 (2018)