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A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs., , , , , , , и . IEEE J. Solid State Circuits, 38 (5): 747-754 (2003)A 700-Mb/s/pin CMOS signaling interface using current integrating receivers., и . IEEE J. Solid State Circuits, 32 (5): 681-690 (1997)Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators., , , , , , , и . ACM Trans. Archit. Code Optim., 20 (2): 26:1-26:26 (июня 2023)AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers., , , , , , , , , и 23 other автор(ы). ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (марта 2023)The Sparse Abstract Machine., , , , , , , и . CoRR, (2022)Fast Extended GCD Calculation for Large Integers for Verifiable Delay Functions., , и . IACR Cryptol. ePrint Arch., (2021)Energy-Performance Tunable Logic., , и . IEEE J. Solid State Circuits, 44 (9): 2554-2567 (2009)CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography., , , , и . IEEE J. Solid State Circuits, 47 (4): 1031-1042 (2012)TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators., , , , и . ASPLOS, стр. 807-820. ACM, (2019)A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs., , , , , , , , , и . DATE, стр. 846-851. IEEE, (2020)