Author of the publication

Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method.

, , , , , , , and . IEEE J. Solid State Circuits, 53 (8): 2389-2398 (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (11): 2411-2424 (2009)A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications., , , , and . ISCAS (2), page 1074-1077. IEEE, (2005)Soft-Event-Upset and Soft-Event-Transient Tolerant CMOS Circuit Design for Low-Voltage Low-Power Wireless IoT Applications., , , and . ICUFN, page 179-181. IEEE, (2019)Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (1): 78-87 (2015)Systolic Array Based Convolutional Neural Network Inference on FPGA., , , and . MCSoC, page 128-133. IEEE, (2022)From English to ASIC: Hardware Implementation with Large Language Model., , , and . CoRR, (2024)An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation., , , , , and . ISCAS, page 608-611. IEEE, (2008)SF-MMCN: A Low Power Re-configurable Server Flow Convolution Neural Network Accelerator., , and . CoRR, (2024)Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design., , , , , , and . ISCAS, page 1803-1806. IEEE, (2007)Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement., and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (1): 141-153 (2018)