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Disambiguation of "Huang, Xuejue"

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Loop-based interconnect modeling and optimization approach for multi-GHz clock network design.

, , , , and . CICC, page 19-22. IEEE, (2002)

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Zheng Huang

Yuejun Huang

Shiwei Huang

Haitao Huang

Jie Huang

 

Other publications of authors with the same name

Frequency-independent equivalent circuit model for on-chip spiral inductors., , , , , , , and . CICC, page 217-220. IEEE, (2002)Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (6): 799-805 (2002)Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (1): 158-162 (2005)Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design., , , , , , and . ICCAD, page 56-61. IEEE Computer Society, (2000)Loop-based interconnect modeling and optimization approach for multigigahertz clock network design., , , , , and . IEEE J. Solid State Circuits, 38 (3): 457-463 (2003)Switch-factor based loop RLC modeling for efficient timing analysis., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (9): 1072-1078 (2005)Loop-based interconnect modeling and optimization approach for multi-GHz clock network design., , , , and . CICC, page 19-22. IEEE, (2002)Improved a priori interconnect predictions and technology extrapolation in the GTX system., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (1): 3-14 (2003)Frequency-independent equivalent-circuit model for on-chip spiral inductors., , , , , , , and . IEEE J. Solid State Circuits, 38 (3): 419-426 (2003)Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion., , , , , , and . ISQED, page 185-190. IEEE Computer Society, (2001)