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Disambiguation of "Chien, Shao-Yi"

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Low-Decoding-Latency Buffer Compression for Graphics Processing Units.

, , and . IEEE Trans. Multim., 14 (2): 250-263 (2012)

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Chieh Chien

Rey-Djin Chien

Chih-Te Chien

Hung-Ju Chien

Ting-Chou Chien

 

Other publications of authors with the same name

Subword Parallel Architecture for Connected Component Labeling and Morphological Operations., and . APCCAS, page 936-939. IEEE, (2006)Partial-result-reuse architecture and its design technique for morphological operations with flat structuring elements., , and . IEEE Trans. Circuits Syst. Video Techn., 15 (9): 1156-1169 (2005)A hardware accelerator for video segmentation using programmable morphology PE array., , and . ISCAS (4), page 341-344. IEEE, (2002)Enhanced temporal error concealment algorithm with edge-sensitive processing order., , , and . ISCAS, page 3466-3469. IEEE, (2008)Fast disparity estimation algorithm for mesh-based stereo image/video compression with two-stage hybrid approach., , , , and . VCIP, volume 5150 of Proceedings of SPIE, page 1521-1530. SPIE, (2003)Distributed video codec with spatiotemporal side information., , , , and . ISCAS, page 1-4. IEEE, (2017)Hardware-Efficient Two-Stage Saliency Detection., , , and . SiPS, page 205-210. IEEE, (2018)Hardware-efficient true motion estimator based on Markov Random Field motion vector correction., , and . VLSI-DAT, page 1-4. IEEE, (2012)Architecture Design of Convolutional Neural Networks for Face Detection on an FPGA Platform., , , , and . SiPS, page 88-93. IEEE, (2018)Architecture Design of Fine Grain Quality Scalable Encoder with CABAC for H.264/AVC Scalable Extension., , , , and . J. Signal Process. Syst., 60 (3): 363-375 (2010)