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Disambiguation of "Castrillón, Jerónimo"

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Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis.

, , , , , , and . Int. J. Embed. Real Time Commun. Syst., 2 (3): 1-20 (2011)

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Jeronimo Castrillon Mazo

Jerónimo Rodríguez

Jerónimo José Granados

Antonio Castrillón H

Elkin Castrillón Oberndorfer

 

Other publications of authors with the same name

RTSim: A Cycle-Accurate Simulator for Racetrack Memories., , , , and . IEEE Comput. Archit. Lett., 18 (1): 43-46 (2019)DownShift: Tuning Shift Reduction With Reliability for Racetrack Memories., , , , and . IEEE Trans. Computers, 72 (9): 2585-2599 (September 2023)Application-aware spinlock control using a hardware scheduler in MPSoC platforms., , , , , , and . ISSoC, page 1-6. IEEE, (2012)Domain-specific Hybrid Mapping for Energy-efficient Baseband Processing in Wireless Networks., , , , and . ACM Trans. Embed. Comput. Syst., 20 (5s): 60:1-60:26 (2021)mpsym: Improving Design-Space Exploration of Clustered Manycores With Arbitrary Topologies., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (6): 1592-1605 (2022)Software Compilation Techniques for MPSoCs., , and . Handbook of Signal Processing Systems, Springer, (2013)Compiler-based graph representations for deep learning models of code., , , and . CC, page 201-211. ACM, (2020)Optimized communication architecture of MPSoCs with a hardware scheduler: A system view., , , , , , and . SoC, page 163-168. IEEE, (2010)Guard the Cache: Dispatch Optimization in a Contextual Role-oriented Language., , and . COP@ECOOP, page 27-34. ACM, (2022)Pruning and Early-Exit Co-Optimization for CNN Acceleration on FPGAs., , , , and . DATE, page 1-6. IEEE, (2023)