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Zero Inclusion Victim: Isolating Core Caches from Inclusive Last-level Cache Evictions.. ISCA, page 71-84. IEEE, (2021)Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors., and . ICPP, page 4. IEEE Computer Society, (2007)Exploiting Dynamic Reuse Probability to Manage Shared Last-level Caches in CPU-GPU Heterogeneous Processors., and . ICS, page 3:1-3:14. ACM, (2016)Performance Evaluation of Concurrent Lock-free Data Structures on GPUs., and . ICPADS, page 53-60. IEEE Computer Society, (2012)Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches.. MICRO, page 401-412. ACM, (2009)Cache Coherence Protocol Design for Active Memory Systems., , and . PDPTA, page 83-89. CSREA Press, (2002)PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches.. HPCA, page 227-238. IEEE Computer Society, (2009)Latency, Occupancy, and Bandwidth in DSM Multiprocessors: A Performance Evaluation., , , , , and . IEEE Trans. Computers, 52 (7): 862-880 (2003)Scavenger: A New Last Level Cache Architecture with Global Block Priority., , , , and . MICRO, page 421-432. IEEE Computer Society, (2007)Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches., , , , and . PACT, page 293-304. ACM, (2012)