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Introduction: Special Section on Architecture of Future Many Core Systems.

, , and . Microprocess. Microsystems, (2016)

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Evaluation of Hardware Data Prefetchers on Server Processors., , , and . ACM Comput. Surv., 52 (3): 52:1-52:29 (2019)High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement., , and . ISLPED, page 79-84. IEEE/ACM, (2011)Comparative Evaluation of Adaptive and Deterministic Routing in the OTIS-Hypercube., and . Asia-Pacific Computer Systems Architecture Conference, volume 3189 of Lecture Notes in Computer Science, page 349-362. Springer, (2004)An efficient DVS scheme for on-chip networks using reconfigurable Virtual Channel allocators., , , and . ISLPED, page 249-254. IEEE, (2015)OSM: Off-Chip Shared Memory for GPUs., , , , , , and . IEEE Trans. Parallel Distributed Syst., 33 (12): 3415-3429 (2022)Introduction: Special Section on Architecture of Future Many Core Systems., , and . Microprocess. Microsystems, (2016)Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems., , and . IEEE Trans. Computers, 65 (4): 1006-1009 (2016)Efficient Nearest-Neighbor Data Sharing in GPUs., , , , , , and . ACM Trans. Archit. Code Optim., 18 (1): 6:1-6:26 (2021)ITAP: Idle-Time-Aware Power Management for GPU Execution Units., , , , , , , , , and . ACM Trans. Archit. Code Optim., 16 (1): 3:1-3:26 (2019)Power-efficient partially-adaptive routing in on-chip mesh networks., , and . ISOCC, page 65-66. IEEE, (2016)