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Disambiguation of "Eide, Geir"

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Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data.

, , , , , , , , , , and . ATS, page 219-224. IEEE Computer Society, (2017)

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Ellen Eide

Geir Volden

Eugen Eide

Bettina Geirhos

Karl Geiringer

 

Other publications of authors with the same name

Design-for-Test Techniques for SoC Designs (Tutorial Abstract).. ISQED, page 7. IEEE Computer Society, (2002)Deriving Feature Fail Rate from Silicon Volume Diagnostics Data., , , , , and . IEEE Des. Test, 30 (4): 26-34 (2013)Employing the STDF V4-2007 Standard for Scan Test Data Logging., , , , , and . IEEE Des. Test, 29 (6): 91-99 (2012)Key Impediments to DFT-Focused Test and How to Overcome Them., and . ITC, page 503-511. IEEE Computer Society, (2003)Open Microphone - My DFT is better than yours ..., and . ITC, page 1285. IEEE Computer Society, (2003)Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs., , , , , , , , , and 3 other author(s). ITC, page 1-10. IEEE, (2020)The Advancement of 1149.10., , , , , , and . ITC-Asia, page 1. IEEE, (2021)ITC 2003 panels: Part 2., , , , and . IEEE Des. Test Comput., 21 (3): 175-176, 261-262 (2004)Embedded Deterministic Test for Low-Cost Manufacturing Test., , , , , , , , , and 1 other author(s). ITC, page 301-310. IEEE Computer Society, (2002)Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data., , , , , , , , , and 1 other author(s). ATS, page 219-224. IEEE Computer Society, (2017)