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Disambiguation of "Du, Jianglin"

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A Compact 0.2-0.3-V Inverse-Class-F23 Oscillator for Low 1/f3 Noise Over Wide Tuning Range.

, , , , , , and . IEEE J. Solid State Circuits, 57 (2): 452-464 (2022)

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Juan Du

Fei Du

Chengran Du

Juan Du

Guohui Du

 

Other publications of authors with the same name

Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS., , , , and . IEEE Open J. Circuits Syst., (2021)A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL., , , , and . IEEE J. Solid State Circuits, 56 (11): 3445-3457 (2021)A Type-II Phase-Tracking Receiver., , , , , , and . IEEE J. Solid State Circuits, 56 (2): 427-439 (2021)Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (3): 973-984 (2022)DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization., , , , and . APCCAS, page 81-84. IEEE, (2019)A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness., , , , , and . IEEE J. Solid State Circuits, 58 (7): 1945-1958 (2023)A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking., , , , , , and . IEEE J. Solid State Circuits, 57 (2): 518-534 (2022)A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS., , , and . CICC, page 1-4. IEEE, (2019)A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB., , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM., , , , , , , and . ISSCC, page 276-278. IEEE, (2020)