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TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design.

, , , , , , , , , , , and . ACM Trans. Reconfigurable Technol. Syst., 16 (4): 63:1-63:31 (December 2023)

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Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU., , , , and . FCCM, page 127-135. IEEE, (2019)RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration., , , , , , , , , and 4 other author(s). ACM Trans. Reconfigurable Technol. Syst., 16 (4): 59:1-59:30 (December 2023)TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2423-2427 (July 2023)Extending High-Level Synthesis for Task-Parallel Programs., , , , , and . FCCM, page 204-213. IEEE, (2021)HeteroRefactor: refactoring for heterogeneous computing with FPGA., , , , , and . ICSE, page 493-505. ACM, (2020)Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication., , , , , and . CoRR, (2021)TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design., , , , , , , , , and 2 other author(s). CoRR, (2022)TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design., , , , , , , , , and 2 other author(s). ACM Trans. Reconfigurable Technol. Syst., 16 (4): 63:1-63:31 (December 2023)AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs., , , , , , , and . FPGA, page 81-92. ACM, (2021)Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication., , , , , and . FPGA, page 65-77. ACM, (2022)