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System Level Design: Orthogonolization of Concerns and Platform-Based Design, , , , и . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (декабря 2000)Certified Timing Verification and the Transition Delay of a Logic Circuit., , , и . DAC, стр. 549-555. IEEE Computer Society Press, (1992)Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation., и . CP, том 2470 из Lecture Notes in Computer Science, стр. 200-215. Springer, (2002)Exploiting Retiming in a Guided Simulation Based Validation Methodology., , и . CHARME, том 1703 из Lecture Notes in Computer Science, стр. 350-353. Springer, (1999)On Solving the Partial MAX-SAT Problem., и . SAT, том 4121 из Lecture Notes in Computer Science, стр. 252-265. Springer, (2006)A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors., и . The Compiler Design Handbook, 2nd ed., CRC Press, (2007)Retiming and resynthesis: optimizing sequential networks with combinational techniques., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (1): 74-84 (1991)Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (5): 568-578 (1993)CNNFlow: Memory-driven Data Flow Optimization for Convolutional Neural Networks., и . ACM Trans. Design Autom. Electr. Syst., 28 (3): 40:1-40:36 (2023)Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface., , , , , , , , , и 3 other автор(ы). ACM Trans. Design Autom. Electr. Syst., 29 (2): 35:1-35:25 (марта 2024)