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Compiler-Assisted Compaction/Restoration of SIMD Instructions.

, , , , , , and . IEEE Trans. Parallel Distributed Syst., 33 (4): 779-791 (2022)

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CONVOLVE: Smart and seamless design of smart edge processors., , , , , , , , , and 18 other author(s). CoRR, (2022)Preface ASAP 2023., , , and . ASAP, page xi. IEEE, (2023)The Entangling Instruction Prefetcher., and . IEEE Comput. Archit. Lett., 19 (2): 84-87 (2020)Efficient thread/page/parallelism autotuning for NUMA systems., , and . ICS, page 342-353. ACM, (2019)Understanding Selective Delay as a Method for Efficient Secure Speculative Execution., , , , and . IEEE Trans. Computers, 69 (11): 1584-1595 (2020)Evaluating the Potential Applications of Quaternary Logic for Approximate Computing., , , and . ACM J. Emerg. Technol. Comput. Syst., 16 (1): 5:1-5:25 (2020)Dynamic and Speculative Polyhedral Parallelization Using Compiler-Generated Skeletons, , , , and . Int. J. Parallel Program., 42 (4): 529--545 (August 2014)CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions., , , , and . PACT, page 1-13. IEEE, (2023)Analysing software prefetching opportunities in hardware transactional memory., , , , , , and . J. Supercomput., 78 (1): 919-944 (2022)Wrong-Path-Aware Entangling Instruction Prefetcher., and . IEEE Trans. Computers, 73 (2): 548-559 (February 2024)