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Compiler-Assisted Compaction/Restoration of SIMD Instructions.

, , , , , , and . IEEE Trans. Parallel Distributed Syst., 33 (4): 779-791 (2022)

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Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies., , , , and . J. Supercomput., 76 (3): 1960-1979 (2020)Novel techniques to improve the performance and the energy of vector architectures.. Polytechnic University of Catalonia, Spain, (2021)VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations., , , , , , , , and . HPCA, page 921-934. IEEE, (2021)POSTER: An Optimized Predication Execution for SIMD Extensions., , , , and . PACT, page 479-480. IEEE, (2019)Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86., , , , , and . Future Gener. Comput. Syst., (2020)PLANAR: a programmable accelerator for near-memory data rearrangement., , , and . ICS, page 164-176. ACM, (2021)POSTER: SPiDRE: Accelerating Sparse Memory Access Patterns., , and . PACT, page 483-484. IEEE, (2019)Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions., , , , and . HPCA, page 717-728. IEEE, (2020)Compiler-Assisted Compaction/Restoration of SIMD Instructions., , , , , , and . IEEE Trans. Parallel Distributed Syst., 33 (4): 779-791 (2022)