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Accelerating low bit-width convolutional neural networks with embedded FPGA.

, , , , and . FPL, page 1-4. IEEE, (2017)

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General switch box modeling and optimization for FPGA routing architectures., , , , and . FPT, page 320-323. IEEE, (2010)An on-line debug method for FPGAs., , and . ASICON, page 484-487. IEEE, (2017)High performance Deformable Part Model accelerator based on FPGA., , , , , and . FPT, page 245-248. IEEE, (2016)Fast Adjustable NPN Classification using Generalized Symmetries., , , and . FPL, page 1-7. IEEE Computer Society, (2018)A scalable hybrid architecture for high performance data-parallel applications., , , , , and . FPT, page 191-194. IEEE, (2017)Online Task Scheduling for Heterogeneous Reconfigurable Systems., , , and . CSCWD (Selected Papers), volume 5236 of Lecture Notes in Computer Science, page 596-607. Springer, (2007)An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis., , , and . ACM Trans. Design Autom. Electr. Syst., 29 (2): 25:1-25:33 (March 2024)An automated test framework for SRAM-based FPGA., , , and . ASICON, page 1-4. IEEE, (2015)Fast Exact NPN Classification by Co-Designing Canonical Form and Its Computation Algorithm., , and . IEEE Trans. Computers, 69 (9): 1293-1307 (2020)RBSA: Range-based simulated annealing for FPGA placement., , , , and . FPT, page 1-8. IEEE, (2017)