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Disambiguation of "Lacaita, Andrea L."

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Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion.

, , , , , and . IEEE J. Solid State Circuits, 37 (8): 1003-1011 (2002)

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L Solymosi

L Bräuer

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L Ruess

 

Other publications of authors with the same name

A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations., , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (9): 3645-3649 (2022)Differential tuning oscillators with reduced flicker noise upconversion., , , , and . ICECS, page 33-36. IEEE, (2004)A multi-tank LC-oscillator microwave oscillator example., , , , and . ICECS, page 29-32. IEEE, (2004)A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs., , , and . MIPRO, page 74-79. IEEE, (2014)Noise Analysis and Minimization in Bang-Bang Digital PLLs., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (11): 835-839 (2009)A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (3): 481-488 (2006)A Background Calibration Technique to Control the Bandwidth of Digital PLLs., , , , , and . IEEE J. Solid State Circuits, 53 (11): 3243-3255 (2018)Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band., , , , and . IEEE J. Solid State Circuits, 48 (10): 2375-2389 (2013)A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop., , , , , and . IEEE J. Solid State Circuits, 50 (11): 2678-2691 (2015)A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration., , , and . IEEE J. Solid State Circuits, 48 (10): 2419-2429 (2013)