( en | de | ru )

 

Disambiguation of "Zorian, Yervant"

Author of the publication

copydeleteadd this publication to your clipboard
Challenges in testing core-based system ICs.

, and . IEEE Commun. Mag., 37 (6): 104-109 (1999)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Zorian, Yervant
add a person with the name Zorian, Yervant
 

Other publications of authors with the same name

Guest Editors' Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory., and . IEEE Des. Test, 34 (1): 6-7 (2017)Guest Editors' Introduction: East Meets West., and . IEEE Des. Test Comput., 13 (1): 5-7 (1996)Guest Editors' Introduction: Design for Yield and Reliability., , , and . IEEE Des. Test Comput., 21 (3): 177-182 (2004)A D&T Roundtable: Testing Mixed Logic and DRAM Chips., , , , , , , and . IEEE Des. Test Comput., 15 (2): 86-92 (1998)Guest Editor's Introduction: Advances in Infrastructure IP.. IEEE Des. Test Comput., 20 (3): 49- (2003)IEEE Std 1500 Enables Modular SoC Testing., and . IEEE Des. Test Comput., 26 (1): 8-17 (2009)Message From the Steering Committee., , , and . IEEE Des. Test Comput., 29 (1): 5 (2012)Design & Test Education in Asia., , , , , and . IEEE Des. Test Comput., 21 (4): 331-338 (2004)Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs., , , , and . ITC, page 1-6. IEEE, (2018)Memory FIT Rate Mitigation Technique for Automotive SoCs., , , , , , , and . ITC, page 1-6. IEEE, (2019)