( en | de | ru )

 

Disambiguation of "Hernández, Carles"

Author of the publication

copydeleteadd this publication to your clipboard
Fault-Tolerant Vertical Link Design for Effective 3D Stacking.

, , , , and . IEEE Comput. Archit. Lett., 10 (2): 41-44 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Stephanie Hernández

Héctor Hernández

Anja Hernández

Daniel Hernández

Onésimo Hernández

 

Other publications of authors with the same name

Enforcing Predictability of Many-Cores With DCFNoC., , , and . IEEE Trans. Computers, 70 (2): 270-283 (2021)Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems., , , , and . RTAS, page 267-278. IEEE Computer Society, (2016)HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem., , , , and . FPL, page 52-59. IEEE, (2021)Resilient random modulo cache memories for probabilistically-analyzable real-time systems., , , and . IOLTS, page 27-32. IEEE, (2016)Enabling High-Performance Crossbars through a Floorplan-Aware Design., , , , and . ICPP, page 269-278. IEEE Computer Society, (2012)SafeSU-2: a Safe Statistics Unit for Space MPSoCs., , , , , , and . DATE, page 1085-1086. IEEE, (2022)A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors., , , , , , , , , and 10 other author(s). ETS, page 1-10. IEEE, (2023)Locality-aware cache random replacement policies., , , and . J. Syst. Archit., (2019)High-Integrity GPU Designs for Critical Real-Time Automotive Systems., , , and . DATE, page 824-829. IEEE, (2019)Random modulo: a new processor cache design for real-time critical systems., , , , and . DAC, page 29:1-29:6. ACM, (2016)