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Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing., , and . ICCD, page 104-111. IEEE Computer Society, (2002)An Asynchronous 2-D Discrete Cosine Transform Chip., , , , and . ASYNC, page 224-. IEEE Computer Society, (1998)Asynchronous Design Using Commercial HDL Synthesis Tools., , , , and . ASYNC, page 114-. IEEE Computer Society, (2000)Checking Delay-Insensitivity: 104 Gates and Beyond., , , , and . ASYNC, page 149-157. IEEE Computer Society, (2002)A Critical Review of the Notion of Algorithm in Computer Science.. ACM Conference on Computer Science, page 1-6. ACM, (1993)A Nonaliasing, Real-Time Spatial Transform Technique.. IEEE Computer Graphics and Applications, 6 (1): 71-80 (1986)Clock-Less DFT-Less Test Strategy for Null Convention Logic., , , and . IEEE Trans. Emerg. Top. Comput., 6 (4): 460-473 (2018)NULL Convention LogicTM: A Complete And Consistent Logic For Asynchronous Digital Circuit Synthesis., and . ASAP, page 261-273. IEEE Computer Society, (1996)Design of asynchronous RISC CPU register-file Write-Back queue., , and . VLSI-SoC, page 31-36. IEEE, (2015)Self-timed automatic test pattern generation for null convention logic., , , and . MWSCAS, page 1-4. IEEE, (2016)