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SDC-based Resource Constrained Scheduling for Quantum Control Architectures.. CoRR, (2022)IP-XACT extensions for Reconfigurable Computing., , , , , and . ASAP, page 215-218. IEEE Computer Society, (2011)High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain., , , , and . EUC, page 138-145. IEEE Computer Society, (2014)Skeleton-Based Synthesis Flow for Computation-in-Memory Architectures., , , , , , and . IEEE Trans. Emerg. Top. Comput., 8 (2): 545-558 (2020)Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays., , , , , and . ACM Trans. Reconfigurable Technol. Syst., 15 (2): 20:1-20:35 (2022)Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs., , , , , and . CoRR, (2021)An Evaluation and Comparison of GPU Hardware and Solver Libraries for Accelerating the OPM Flow Reservoir Simulator., , , , and . CoRR, (2023)OpenQL : A Portable Quantum Programming Framework for Quantum Accelerators., , , , , , , , and . CoRR, (2020)OpenQL: A Portable Quantum Programming Framework for Quantum Accelerators., , , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (1): 13:1-13:24 (2022)Sparstition: A Partitioning Scheme for Large-Scale Sparse Matrix Vector Multiplication on FPGA., , , and . ASAP, page 51-58. IEEE, (2019)