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Adding static data dependence collapsing to a high-performance instruction scheduler.

, , , и . J. Syst. Archit., 47 (8): 727-745 (2001)

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Другие публикации лиц с тем же именем

Adding static data dependence collapsing to a high-performance instruction scheduler., , , и . J. Syst. Archit., 47 (8): 727-745 (2001)An explicitly declared delayed-branch mechanism for a superscalar architecture., и . Microprocess. Microprogramming, 40 (10-12): 677-680 (1994)Cached Two-Level Adaptive Branch Predictors with Multiple Stages., , и . ARCS, том 2299 из Lecture Notes in Computer Science, стр. 179-194. Springer, (2002)Investigating the Limits of Fine-Grained Parallelism in a Statically Scheduled Superscalar Architecture., и . Euro-Par, Vol. II, том 1124 из Lecture Notes in Computer Science, стр. 779-788. Springer, (1996)Static instruction scheduling for the HARP multiple-instruction-issue architecture., , , и . Microprocess. Microsystems, 17 (7): 415-424 (1993)A superscalar architecture to exploit instruction level parallelism., , , , и . Microprocess. Microsystems, 20 (7): 391-400 (1997)How useful are complex instructions? A case study using the M68000., и . Microprocessing and Microprogramming, 29 (4): 247-259 (1990)Applying Caching to Two-Level Adaptive Branch Prediction., , , и . DSD, стр. 186-193. IEEE Computer Society, (2001)Static Scheduling for Out-of-order Instruction Issue Processors., , и . ACAC, стр. 90-96. IEEE Computer Society, (2000)Two-level branch prediction using neural networks., , , , , и . J. Syst. Archit., 49 (12-15): 557-570 (2003)