( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Recovery-driven design: a power minimization methodology for error-tolerant processor modules.

, , , и . DAC, стр. 825-830. ACM, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Andrew Huvos

Andrew Lee

Andrew Cato

Andrew Singer

Andrew Torda

 

Другие публикации лиц с тем же именем

Optimal robust path planning in general environments., , и . IEEE Trans. Robotics Autom., 9 (6): 775-784 (1993)The Future of Signoff.. IEEE Des. Test Comput., 28 (3): 86-89 (2011)Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs., , , , , , и . IEEE Des. Test Comput., 24 (1): 83-93 (2007)How much variability can designers tolerate?. IEEE Des. Test Comput., 20 (6): 96-97 (2003)Evaluation of the new OASIS format for layout fill compression., , , , и . ICECS, стр. 377-382. IEEE, (2004)Optimal partitioners and end-case placers for standard-cell layout., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (11): 1304-1313 (2000)Multilevel circuit partitioning., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (8): 655-667 (1998)Prim-Dijkstra tradeoffs for improved performance-driven routing tree design., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (7): 890-896 (1995)On wirelength estimations for row-based placement., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (9): 1265-1278 (1999)Provably good performance-driven global routing., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (6): 739-752 (1992)