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Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths., , , , и . ASP-DAC, стр. 350-355. IEEE, (2013)Effective free space management for cut-based placement via analytical constraint generation., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (10): 1343-1353 (2003)Porosity-aware buffered Steiner tree construction., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (4): 517-526 (2004)Optimal path routing in single- and multiple-clock domain systems., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (11): 1580-1588 (2003)Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography., , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 726-739 (2015)Accurate estimation of global buffer delay within a floorplan., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 1140-1145 (2006)MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes., , , , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (6): 1237-1250 (2018)On the Minimum Density Interconnection Tree Problem., , , , и . VLSI Design, 2 (2): 157-169 (1994)Closed-form delay and slew metrics made easy., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (12): 1661-1669 (2004)Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (4): 509-516 (2004)