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DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (7): 1325-1334 (2021)

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Enabling efficient fine-grained DRAM activations with interleaved I/O., and . ISLPED, page 1-6. IEEE, (2017)Sanitizer: Mitigating the Impact of Expensive ECC Checks on STT-MRAM Based Main Memories., , , and . IEEE Trans. Computers, 67 (6): 847-860 (2018)ClusCross: a new topology for silicon interposer-based network-on-chip., and . NOCS, page 7:1-7:8. ACM, (2019)Scrabble: A Fine-Grained Cache with Adaptive Merged Block., , and . IEEE Trans. Computers, 69 (1): 112-125 (2020)HIRAC: A Hierarchical Accelerator with Sorting-based Packing for SpGEMMs in DNN Applications., , , and . HPCA, page 247-258. IEEE, (2023)Efficient and Accurate Computational Model of Neuron with Spike Frequency Adaptation., , , , , and . EMBC, page 6496-6499. IEEE, (2021)Optimizing Recurrent Spiking Neural Networks with Small Time Constants for Temporal Tasks., , , , and . ICONS, page 6:1-6:8. ACM, (2022)Languages Must Expose Memory Heterogeneity., , , and . MEMSYS, page 251-256. ACM, (2016)RnR: A Software-Assisted Record-and-Replay Hardware Prefetcher., , , and . MICRO, page 609-621. IEEE, (2020)Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing., , , , , and . IEEE Micro, 35 (5): 62-71 (2015)