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NeuroTrainer: An Intelligent Memory Module for Deep Learning Training., , , and . CoRR, (2017)Using rapid prototyping in computer architecture design laboratories., , , and . WCAE@HPCA, page 4. ACM, (1996)Parallel image normalization on a mesh connected array processor., , and . Pattern Recognit., 20 (1): 115-124 (1987)Formulation of parallel image processing tasks., and . Pattern Recognit. Lett., 2 (4): 261-270 (1984)A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective., , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (5): 809-817 (2011)Algebraic Properties of some Parallel Processor Interconnection Networks., and . ICDE, page 611-618. IEEE Computer Society, (1984)Centralized buffer router: A low latency, low power router for high radix NOCs., and . NOCS, page 1-8. IEEE, (2013)A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks., and . IEEE Trans. Parallel Distributed Syst., 6 (5): 482-497 (1995)Understanding Energy Aspects of Processing-near-Memory for HPC Workloads., , , and . MEMSYS, page 276-282. ACM, (2015)Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the Uncore., , and . MEMSYS, page 11-21. ACM, (2015)