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Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis.

, , , и . PATMOS, том 2799 из Lecture Notes in Computer Science, стр. 617-627. Springer, (2003)

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José-Manuel Ruiz-Marcos

Jose Miguel Ruiz

José Francisco Ruíz Borge

Margarita Ruiz Kolb

Javier Ruiz-del-Solar

 

Другие публикации лиц с тем же именем

Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis., , , и . PATMOS, том 2799 из Lecture Notes in Computer Science, стр. 617-627. Springer, (2003)Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (1): 60-73 (2009)Behavioural Scheduling to Balance the Bit-Level Computational Effort., , , и . ISVLSI, стр. 99-104. IEEE Computer Society, (2004)Performance-driven scheduling of behavioural specifications., , , и . Integr., 42 (3): 294-303 (2009)Arrival time aware scheduling to minimize clock cycle length., , , и . ASP-DAC, стр. 1018-1021. ACM Press, (2005)Pre-synthesis optimization of multiplications to improve circuit performance., , , и . DATE, стр. 1306-1311. European Design and Automation Association, Leuven, Belgium, (2006)Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis, , , и . CoRR, (2007)Subword Switching Activity Minimization to Optimize Dynamic Power Consumption., , , и . IEEE Des. Test Comput., 26 (4): 68-77 (2009)Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits., , , и . DSD, стр. 464-471. IEEE Computer Society, (2008)Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioral Synthesis., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (9): 1589-1601 (2007)