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Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis., , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 617-627. Springer, (2003)Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (1): 60-73 (2009)Behavioural Scheduling to Balance the Bit-Level Computational Effort., , , and . ISVLSI, page 99-104. IEEE Computer Society, (2004)Arrival time aware scheduling to minimize clock cycle length., , , and . ASP-DAC, page 1018-1021. ACM Press, (2005)Performance-driven scheduling of behavioural specifications., , , and . Integr., 42 (3): 294-303 (2009)Pre-synthesis optimization of multiplications to improve circuit performance., , , and . DATE, page 1306-1311. European Design and Automation Association, Leuven, Belgium, (2006)Subword Switching Activity Minimization to Optimize Dynamic Power Consumption., , , and . IEEE Des. Test Comput., 26 (4): 68-77 (2009)Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis, , , and . CoRR, (2007)Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits., , , and . DSD, page 464-471. IEEE Computer Society, (2008)Bitwise scheduling to balance the computational cost of behavioral specifications., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (1): 31-46 (2006)