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Disambiguation of "Hwang, Sewook"

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A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection.

, , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (2): 268-278 (2013)

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Hak Hwang

Sungil Hwang

Byung Kook Hwang

Giin-Tarng Hwang

Kyung-Yub Hwang

 

Other publications of authors with the same name

A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile., , , , and . IEEE J. Solid State Circuits, 47 (5): 1199-1208 (2012)17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces., , , , and . ISSCC, page 1-3. IEEE, (2015)An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface., , , , , , , and . ISSCC, page 312-313. IEEE, (2013)A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (8): 2768-2777 (2016)12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces., , , , , , and . IEEE J. Solid State Circuits, 54 (2): 463-475 (2019)A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (2): 192-196 (2019)A 0.076mm2 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS., , , , and . ISSCC, page 360-362. IEEE, (2011)A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector., , , , , , and . IEEE Access, (2021)A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (10): 2691-2702 (2017)A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (2): 303-313 (2013)