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Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity., , , , , , , and . ISCAS (1), page 110-113. IEEE, (1999)Prioritised ceteris paribus logic for counterfactual reasoning., and . Synthese, 195 (4): 1681-1703 (2018)Example-based programming: a pertinent visual approach for learning to program., , and . AVI, page 358-361. ACM Press, (2004)Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 32 (1): 116-127 (January 2024)DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (7): 1325-1334 (2021)Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (6): 2256-2260 (June 2023)An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization., , , , , , , and . J. Electron. Test., 32 (6): 721-733 (2016)A Scan-BIST Structure to Test Delay Faults in Sequential Circuits., , , , and . J. Electron. Test., 14 (1-2): 95-102 (1999)On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits., , , and . J. Electron. Test., 36 (1): 33-46 (2020)A Ring Architecture Strategy for BIST Test Pattern Generation., , , and . J. Electron. Test., 19 (3): 223-231 (2003)