Author of the publication

Optimal Backgrounds Selection for Multi Run Memory Testing.

, and . DDECS, page 332-338. IEEE Computer Society, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Analysis of multibackground memory testing techniques.. Int. J. Appl. Math. Comput. Sci., 20 (1): 191-205 (2010)Optimal Backgrounds Selection for Multi Run Memory Testing., and . DDECS, page 332-338. IEEE Computer Society, (2008)Universal Address Sequence Generator for Memory Built-in Self-test., , and . CoRR, (2022)Transparent Memory Tests Based on the Double Address Sequences., and . Entropy, 23 (7): 894 (2021)Antirandom Test Vectors for BIST in Hardware/Software Systems., and . Fundam. Informaticae, 119 (2): 163-185 (2012)Iterative Antirandom Testing., and . J. Electron. Test., 28 (3): 301-315 (2012)Optimal Controlled Random Tests., and . CISIM, volume 10244 of Lecture Notes in Computer Science, page 27-38. Springer, (2017)Impact of the address changing on the detection of pattern sensitive faults., , and . Information Processing and Security Systems, Springer, (2005)Multi Background Memory Testing., , and . CISIM, page 155-156. IEEE Computer Society, (2008)Address Sequences Generation for Multiple Run Memory Testing., , and . CISIM, page 341-344. IEEE Computer Society, (2007)